In the population of integrated circuit chip carriers, including thermally conductive modules, ceramic substrates, and polymeric substrates, it is necessary to minimize the shipment of modules with defective integrated circuit chips or other components. Integrated circuit chips in particular are subjected to various wafer level tests during various stages of fabrication, typically prior to dicing. After dicing, it is difficult and expensive to test these integrated circuit chips. One reason for this is that the integrated circuit chip must be tested through its pins and contacts or pads before populating of the carrier, card, board or the like.
Typically, integrated circuit chips are attached to a chip carrier, thermally conductive module chip carrier, circuit card or board, e.g., by solder bonding, brazing, controlled collapse chip connect, wire lead bonding, metal bump bonding, tape automated bonding, or the like. The chip is then tested as part of an assembly and when a fault is found, the chip is removed from the card or board.
When debugging cards containing circuit packages with many surface mount leads, it is difficult to apply and hold a test clip to the leads while ensuring that a reliable connection is made to the leads. Significant time can be wasted reapplying a test clip that has partially or completely slipped off the surface mount leads, whether by a slight bump or tug on the test clip wires or possibly because friction/clamping engagement to the leads failed due to imperfections in the leads. If the test clip becomes disconnected, a long test sequence might have to be restarted. Further, an undetected poor or open contact can cause a false signal level at a metering device leading to a false conclusion about the integrated circuit component or the card itself. For example, oxidation of a surface mount lead or its solder connection to the card can inhibit/prevent electrical connection of the test clip to the lead, thereby potentially resulting in a defective test result.
Thus, an enhanced method/apparatus is needed in the art for a means for rapid, reproducible, electrical connection of a test clip to the leads of an integrated circuit component mounted on a multi-component card for high throughput testing of the integrated circuit components of the card.